Mitigating charge spill-back induced image lag with a multi-level transfer gate pulse in PPD image sensors

Ivory, James; Stefanov, Konstantin D. and Holland, Andrew D. (2020). Mitigating charge spill-back induced image lag with a multi-level transfer gate pulse in PPD image sensors. In: X-Ray, Optical, and Infrared Detectors for Astronomy IX (Holland, Andrew D. and Beletic, James eds.), Proceedings of SPIE, SPIE, Bellingham, WA.

DOI: https://doi.org/10.1117/12.2562529

Abstract

A new method for minimizing image lag due to charge spill-back has been developed for pinned photodiode CMOS image sensors. The proposed method involves the use of multi-level transfer gate voltage during a single charge transfer period. Measurement results show that the new transfer process maintains the lower values for image lag at low signal levels that a high transfer gate voltage grants, whilst simultaneously preserving the later onset of spill-back dominated lag that a lower transfer gate voltage allows.

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About

• Item ORO ID
• 74611
• Item Type
• Conference or Workshop Item
• Keywords
• CMOS; transfer gate voltage; charge spillback; image lag
• Academic Unit or School
• Faculty of Science, Technology, Engineering and Mathematics (STEM) > Physical Sciences
  Faculty of Science, Technology, Engineering and Mathematics (STEM)
• Research Group
• Centre for Electronic Imaging (CEI)
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• Copyright Holders
• © 2020 Society of Photo-Optical Instrumentation Engineers (SPIE)
• Depositing User
• Konstantin Stefanov