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Electron Multiplying Low-Voltage CCD With Increased Gain

Stefanov, Konstantin D.; Dunford, Alice and Holland, Andrew D. (2018). Electron Multiplying Low-Voltage CCD With Increased Gain. IEEE Transactions on Electron Devices, 65(7) pp. 2990–2996.

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DOI (Digital Object Identifier) Link: https://doi.org/10.1109/TED.2018.2839023
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Abstract

Novel designs for the gain elements in electron multiplying (EM) CCDs have been implemented in a device manufactured in a low voltage CMOS process. Derived with help from TCAD simulations, the designs employ modified gate geometries in order to significantly increase the EM gain over traditional structures. Two new EM elements have been demonstrated with an order of magnitude higher gain than the typical rectangular gate designs, achieved over 100 amplifying stages and without an increase in the electric field. The principles presented in this work can be used in CMOS and CCD imagers employing electron multiplication in order to boost the gain and reduce undesirable effects such as clock-induced charge generation and gain ageing.

Item Type: Journal Item
Copyright Holders: 2018 IEEE
ISSN: 0018-9383
Keywords: Logic gates; Impact ionization; Electric potential; Charge coupled devices; Aging; Imaging
Academic Unit/School: Faculty of Science, Technology, Engineering and Mathematics (STEM) > Physical Sciences
Faculty of Science, Technology, Engineering and Mathematics (STEM)
Research Group: Centre for Electronic Imaging (CEI)
Item ID: 55541
Depositing User: Konstantin Stefanov
Date Deposited: 20 Jun 2018 15:39
Last Modified: 07 May 2019 17:36
URI: http://oro.open.ac.uk/id/eprint/55541
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