An analog neural network processor with programmable topology

Boser, Bernhard E.; Säckinger, Eduard; Bromley, Jane M.; Le Cun, Yann and Jackel, Lawrence D. (1991). An analog neural network processor with programmable topology. IEEE Journal of Solid-State Circuits, 26(12) pp. 2017–2025.

DOI: https://doi.org/10.1109/4.104196

Abstract

The architecture, implementation, and applications of a special-purpose neural network processor are described. The chip performs over 2000 multiplications and additions simultaneously. Its data path is particularly suitable for the convolutional topologies that are typical in classification networks, but can also be configured for fully connected or feedback topologies. Resources can be multiplexed to permit implementation of networks with several hundreds of thousands of connections on a single chip. Computations are performed with 6 b accuracy for the weights and 3 b for the neuron states. Analog processing is used internally for reduced power dissipation and higher density, but all input/output is digital to simplify system integration. The practicality of the chip is demonstrated with an implementation of a neural network for optical character recognition. This network contains over 130000 connections and was evaluated in 1 ms

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