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Principles for the design of a distributed memory architecture for parallel graph reduction

Bevan, D. I.; Burn, G. L.; Karia, R. J. and Robson, J. D. (1989). Principles for the design of a distributed memory architecture for parallel graph reduction. The Computer Journal, 32(5) pp. 461–469.

URL: http://comjnl.oxfordjournals.org/content/32/5/461....
DOI (Digital Object Identifier) Link: http://dx.doi.org/10.1093/comjnl/32.5.461
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Abstract

Many models for the parallel reduction of lazy functional languages have been proposed in the literature. The one we have chosen to implement is based on evaluation transformers. An evaluation transformer says how much evaluation can be done to an argument expression in a function application, given the amount of evaluation that can be done to the application.Rather than just selecting a distributed memory architecture and trying to support parallel graph reduction, we investigate the implications of a minimally specified distributed memory architecture for parallel graph reduction.The results of the investigation are incorporated into an abstract machine which is able to support the communication and synchronisation needs of the parallel reduction model on a distributed memory architecture. Certain flags are needed on the nodes in the program graph in order to support the model. These are motivated and described.

Item Type: Journal Article
Copyright Holders: 1989 Oxford University Press
ISSN: 1460-2067
Academic Unit/Department: Mathematics, Computing and Technology
Item ID: 33681
Depositing User: David Bevan
Date Deposited: 31 May 2012 08:56
Last Modified: 31 May 2012 08:56
URI: http://oro.open.ac.uk/id/eprint/33681
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